1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a plurality of wiring layers in a multi-layered structure by which a bypass capacitor is defined, and a method of fabricating the same.
2. Description of the Related Art
There has been known a large scaled integrated circuit (LSI) chip as a semiconductor device including a plurality of wiring layers in a multi-layered structure, and including an inner area centrally at a surface and a pad area around the inner area.
FIGS. 1A and 1B illustrate a conventional LSI chip. FIG. 1A is a top plan view of the same, and FIG. 1B is an enlarged view of an area M in FIG. 1A.
As illustrated in FIG. 1A, LSI chip 1 is comprised of an inner area 2 located centrally at a surface of LSI chip 1, an input/output area 3 located around the inner area 2, and a pad area 4 located around the input/output area 3.
In the input/output area 3, a plurality of input/output terminal 5 is arranged surrounding the inner area 2. In the pad area 4, a plurality of pads 6 is arranged surrounding the input/output area 3.
In the input/output area 3, there are formed a first wire 7 in the form of a square, surrounding the inner area 2, and a second wire 8 in the form of a square, surrounding the first wire 7. The first wire 7 is electrically connected to a voltage source (not illustrated), and the second wire 8 is grounded.
Any wiring layers are not formed below the pads 6 in the pad area 4. This is because if wiring layers are formed below the pads 6, a force may be exerted on the pads 6 in a step of wire-bonding, resulting in that the pads 6 may be damaged.
As illustrated in FIG. 1B, the pads 6 are electrically connected to the input/output terminal 5, the first wire 7 or the second wire 8 through a via contact 9. Hereinbelow, a pad 6 electrically connected to the input/output terminal 5 is called a signal pad 6a, a pad 6 electrically connected to the first wire 7 is called a VDD pad 6b, and a pad 6 electrically connected to the second wire 8 is called a GND pad 6c. 
Each of the first and second wires 7 and 8 is comprised of a plurality of metal wire layers in a multi-layered structure in the input/output area 3. In order to ensure to apply a source voltage to a transistor fabricated in the input/output area 3, the first wire 7 is formed just above a p-channel region in an input/output buffer, and the second wire 8 is formed separately from the first wire 7 just above a n-channel region in an input/output buffer.
However, the first and second wires 7 and 8 are not designed to have a structure suitable for defining a bypass capacitor therein for suppressing noises in a power source line to thereby stabilize a voltage. Accordingly, in order to ensure a resistance to such noises and an operation at a high rate, it would be necessary to form quite a lot of the VDD pads 6b and the GND) pads 6c. 
This is because, with a size of a chip being smaller and smaller and an operation speed being higher and higher, it becomes more and more difficult for a conventional power source to guarantee a resistance to noises and a radio-frequency characteristic to be in an allowable range. Since it becomes difficult to reduce an impedance in a conventional power source in a chip fabricated smaller and smaller, it would be unavoidable to increase the VDD pads 6b and the GND pads 6c in order to ensure a high speed operation of a chip.
A bypass capacitor is often formed around a chip on a substrate. However, such a bypass capacitor formed on a substrate would be a bar to an increase in a density at which components are mounted on a substrate.
Japanese Unexamined Patent Publication No. 5-55380 has suggested a semiconductor integrated circuit device including a plurality of wiring layers, characterized in that a first wiring layer electrically connected to a voltage source is formed all over at least one of the wiring layers, and that a second wiring layer grounded is formed all over at least one of said wiring layers except the first wiring layer.
Japanese Unexamined Patent Publication No. 9-307067 has suggested a semi-custom semiconductor integrated circuit device including a capacitor formed in a non-used bonding pad area. The capacitor has at least three wiring layers and insulating layers sandwiched between wiring layers. A first voltage is applied to a lower wiring layer, a second voltage is applied to an intermediate wiring layer, and the first voltage or a third voltage is applied to an upper wiring layer.
However, the above-mentioned problems remain unsolved even in those Publications.
In view of the above-mentioned problems in the conventional semiconductor devices, it is an object of the present invention to provide a semiconductor device which is capable of defining a bypass capacitor without occupying a space to thereby enhance a resistance to noises and a radio-frequency characteristic in a power source line without increasing pads in number.
In one aspect of the present invention, there is provided a semiconductor device having a plurality of wiring layers in a multi-layered structure, the semiconductor device including an inner area at a surface and a pad area surrounding the inner area therein, the semiconductor device including a device fabricated below the pad area.
For instance, the device is comprised of a bypass capacitor, a protection device, or an input/output device alone or in combination.
The semiconductor device may further include a second device fabricated below the device, the device being comprised of a bypass capacitor, the second device being comprised of at least one of a protection device and an input/output device.
It is preferable that the bypass capacitor is comprised of metal wire layers arranged below the pad area.
For instance, each of the metal wire layers may be comprised of a first wire and a second wire with an interlayer insulating layer being sandwiched therebetween, the first wire being electrically connected to a voltage source, the second wire being grounded.
As an alternative, each of the metal wire layers may be comprised of a first comb-shaped wire being electrically connected to a voltage source and a second comb-shaped wire being grounded, the first and second wires being arranged such that teeth of the first comb-shaped wire are located between teeth of the second comb-shaped wire in the same plane.
The semiconductor device may further include at least one of first to fourth pads in the pad area, the first pad being electrically connected to the input/output device, the second pad being electrically connected to the first wire, the third pad being electrically connected to the second wire, the fourth pad being not electrically connected to the input/output device, the first wire and the second wire.
There is further provided a semiconductor device having a plurality of wiring layers in a multi-layered structure, the semiconductor device including an inner area at a surface, an input/output area surrounding the inner area therein, and a pad area surrounding the input/output area therein, the semiconductor device including a plurality of input/output terminals in the input/output area, and a plurality of pads in the pad area, the semiconductor device including (a) a first source voltage wire being electrically connected to a voltage source and surrounding the inner area in the pad area, and (b) a first ground wire being grounded and surrounding the first source voltage wire in the pad area, each of the pads being electrically connected to any one of the input/output terminals, the first source voltage wire, and the first ground wire, the first source voltage wire being comprised of a plurality of first metal wiring layers in a multi-layered structure, the first metal wiring layers being electrically connected to one another through via-holes formed through first interlayer insulating films sandwiched between the first metal wiring layers, the first ground wire being comprised of a plurality of second metal wiring layers in a multi-layered structure, the second metal wing layers being electrically connected to one another through via-holes formed through the first interlayer insulating films, each of the first metal wiring layers and each of the second metal wiring layers being formed in the same layer, vertically adjacent first and second metal wiring layers with one of the first interlayer insulating films being sandwiched therebetween, among the first and second metal wiring layers, defining a bypass capacitor.
It is preferable that the semiconductor device further includes (c) a second source voltage wire being electrically connected to a voltage source and surrounding the inner area in the input/output area, and (d) a second ground wire being grounded and surrounding the second source voltage wire in the input/output area, the second source voltage wire being comprised of a plurality of third metal wiring layers in a multi-layered structure, the third metal wiring layers being electrically connected to one another through via-holes formed through second interlayer insulating films sandwiched between the third metal wiring layers, the second ground wire being comprised of a plurality of fourth metal wiring layers in a multi-layered structure, the fourth metal wiring layers being electrically connected to one another through via-holes formed through the second interlayer insulating films, each of the third metal wiring layers and each of the fourth metal wiring layers being formed in the same layer, vertically adjacent third and fourth metal wiring layers with one of the second interlayer insulating films being sandwiched therebetween, among the third and fourth metal wiring layers, defining a bypass capacitor.
It is preferable that the first source voltage wire is electrically connected to the second source voltage wire, and the first ground wire is electrically connected to the second ground wire.
It is preferable that the first source voltage wire is comprised of a first comb-shaped wire being electrically connected to a voltage source, and the first ground wire is comprised of a second comb-shaped wire being grounded, the second source voltage wire is comprised of a third comb-shaped wire being electrically connected to a voltage source, and the second ground wire is comprised of a fourth comb-shaped wire being grounded, the first and second wires being arranged such that teeth of the first comb-shaped wire are located between teeth of the second comb-shaped wire in the same plane, the third and fourth wires being arranged such that teeth of the third comb-shaped wire are located between teeth of the fourth comb-shaped wire in the same plane.
It is preferable that the first source voltage wire is electrically connected to the second source voltage wire, and the first ground wire is electrically connected to the second ground wire.
The semiconductor device may further include a protection device fabricated below the bypass capacitor, the protection device including (a) a substrate formed at a surface with a first well having a first electrical conductivity and a second well having a second electrical conductivity, (b) a first interlayer insulating film formed on the substrate, (c) a first layer formed on the first interlayer insulating film, (d) a second interlayer insulating film formed on the first layer, and (e) a signal wiring layer formed on the second interlayer insulating film, the first layer including one of the first metal wiring layers, one of the second metal wiring layers, and a second signal wiring layer all electrically connected to the first or second well through via-holes formed through the first interlayer insulating film, the second signal wiring layer being electrically connected to the signal wiring layer through via-holes formed through the second interlayer insulating film.
It is preferable that the input/output area has an extended portion located below the pad area, the extended portion including (a) a substrate formed at a surface with a first well having a first electrical conductivity and a second well having a second electrical conductivity, (b) a first interlayer insulating film formed on the substrate, (c) a first layer formed on the first interlayer insulating film, (d) a second interlayer insulating film formed on the first layer, and (e) a signal wiring layer formed on second interlayer insulating film, the first layer including one of the first metal wiring layers electrically connected to the first well through a via-hole formed through the first interlayer insulating film, one of the second metal wiring layers electrically connected to the second well through a via-hole formed through the first interlayer insulating film, and a second signal wiring layer electrically connected to the first or second well through via-holes formed through the first interlayer insulating film, the second signal wiring layer being electrically connected to the signal wiring layer through via-holes formed through the second interlayer insulating film.
There is still further provided a semiconductor device having a plurality of wiring layers in a multi-layered structure, the semiconductor device including an inner area at a surface, an input/output area surrounding the inner area therein, and a pad area surrounding the input/output area therein, the semiconductor device including a plurality of input/output terminals in the input/output area, and a plurality of pads in the pad area, the semiconductor device including (a) a first source voltage wire being electrically connected to a voltage source and surrounding the inner area in the pad area, and (b) a first ground wire being grounded and surrounding the first source voltage wire in the pad area, each of the pads being electrically connected to any one of the input/output terminals, the first source voltage wire, and the first ground wire, the semiconductor device including a protection device fabricated below the pad area, the protection device including (a) a substrate formed at a surface with a first well having a first electrical conductivity and a second well having a second electrical conductivity, (b) a first interlayer insulating film formed on the substrate, (c) a first layer formed on the first interlayer insulating film, (d) a second interlayer insulating film formed on the first layer, and (e) a signal wiring layer formed on second interlayer insulating film, the first layer including one of the first metal wiring layers, one of the second metal wiring layers, and a second signal wiring layer all electrically connected to the first or second well through via-holes formed through the first interlayer insulating film, the second signal wiring layer being electrically connected to the signal wiring layer through via holes formed through the second interlayer insulating film.
There is yet further provided a semiconductor device having a plurality of wiring layers in a multi-layered structure, the semiconductor device including an inner area at a surface, an input/output area surrounding the inner area therein, and a pad area surrounding the input/output area therein, the semiconductor device including a plurality of input/output terminals in the input/output area, and a plurality of pads in the pad area, the semiconductor device including (a) a first source voltage wire being electrically connected to a voltage source and surrounding the inner area in the pad area, and (b) a first ground wire being grounded and surrounding the first source voltage wire in the pad area, each of the pads being electrically connected to any one of the input/output terminals, the first source voltage wire, and the first ground wire, the input/output area having an extended portion located below the pad area, the extended portion including (a) a substrate formed at a surface with a first well having a first electrical conductivity and a second well having a second electrical conductivity, (b) a first interlayer insulating film formed on the substrate, (c) a first layer formed on the first interlayer insulating film, (d) a second interlayer insulating film formed on the first layer, and (e) a signal wiring layer formed on second interlayer insulating film, the first layer including one of the first metal wiring layers electrically connected to the first well through a via-hole formed through the first interlayer insulating film, one of the second metal wiring layers electrically connected to the second well through a via-hole formed through the first interlayer insulating film, and a second signal wiring layer electrically connected to the first or second well through via-holes formed through the first interlayer insulating film, the second signal wiring layer being electrically connected to the signal wiring layer through via-holes formed through the second interlayer insulating film.
In another aspect of the present invention, there is provided a method of fabricating a semiconductor device having a plurality of wiring layers in a multi-layered structure, and having an inner area at a surface and a pad area surrounding the inner area therein, the method including the steps of (a) forming the inner area, and (b) fabricating a device below the pad area, the steps (a) and (b) being to be concurrently carried out.
For instance, at least one of a bypass capacitor, a protection device, and an input/output device is fabricated as the device in the step (b).
The method may further include the step of (c) fabricating a second device below the device.
It is preferable that the step (c) is carried out concurrently with the steps (a) and (b).
It is preferable that a bypass capacitor is fabricated as the device in the step (b), and at least one of a protection device and an input/output device is fabricated as the second device in the step (c).
The advantages obtained by the aforementioned present invention will be described hereinbelow.
In the semiconductor device in accordance with the present invention, a device is fabricated below the pad area. Accordingly, a device such as a bypass capacitor can be fabricated without occupying a space. The thus fabricated bypass capacitor would enhance a resistance to noises and a radio-frequency characteristic in a power source line without increasing pads in number.